A structured ASIC (application specific integrated circuit) is a large-scale, high-complexity semiconductor device that includes one or more of the following elements: (1) memory; (2) a customizable array of transistors; (3) an IP (intellectual property) block; (4) a processor, e.g., an ESP (embedded standard product); (5) an embedded programmable logic block; and (6) interconnect. RapidChip™ developed by LSI Logic Corp. is an example of a structured ASIC.
Structured ASIC based IC design is a powerful concept for coping with the increased pressure on time-to-market, design and manufacturing costs. The basic idea behind structured ASIC based IC design is to avoid designing a chip from scratch. Some portion of the chip's architecture is predefined for a specific type of application. Through extensive design reuse, the structured ASIC based IC design may provide faster time-to-market and reduce design cost.
Under a structured ASIC approach, there may exist two distinct steps entailed in creating a final end-user product: a prefabrication step and a customization step. In a prefabrication step, a slice is built on a wafer. A slice is a pre-manufactured chip in which all silicon layers have been built, leaving the top metal layers to be completed with the customer's unique IP. For example, RapidSlice™ developed by LSI Logic Corp. is an example of a slice. One or more slices may be built on a single wafer. It is understood that a slice may include one or more bottom metal layers or may include no metal layers at all. In a preferred embodiment of the prefabrication step, the diffusion processes and the early-metal steps are carried out in a wafer fab. That is, the base characteristics, in terms of the IP, the processors, the memory, the interconnect, the programmable logic and the customizable transistor array, are all laid down and prediffused, and the early-metal components of the stack are manufactured. However, a slice is still fully decoupled because the customer has not yet introduced the function into the slice. In a customization step, metal layers (or late-metal components) are laid down, which couple the elements that make up the slice built in the wafer fab, and the customizable transistor array is configured and given its characteristic function.
Development of a structured ASIC often creates a need not only for a demonstration platform but also for a development and proof of concept platform. Because the variation in customer requirements may be significant, particularly in the software requirements and in the type and quantity of interfaces that require support, the cost in dollars and time of the platform should be minimized for marketability. Conventionally, a demonstration and development platform may involve the following methods: (1) software simulation (However, such a method may be custom developed per project and tends to execute very slowly. Moreover, there is no proof of actual hardware); (2) board based solutions using standard products (Such a method may prove out designs at or near speed. However, the board is seldom based on final hardware and often does not show the platform itself or its IP. Moreover, each board may be custom developed); and (3) standard product based upon a RapidSlice™ (This method may show the RapidSlice™ technology, but may not be adaptable to customer's proof of concept, development, or demonstration).
Thus, it would be desirable to provide a customizable development and demonstration platform, which may permit flexible use for a variety of development and demonstration needs, and may allow fast execution compared to software simulation and low cost compared to multiple custom developments. Such a platform may use the same technology and IP as used in the final, custom device and may have demo applications software readily available at relatively low cost and engineering effort.